EP1830-20CFN vs EP1810LI-35 Comparación
Comparación detallada lado a lado de EP1830-20CFN por Texas Instruments y EP1810LI-35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1830-20CFN | EP1810LI-35 |
|---|---|---|
| Marca | Texas Instruments | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $78,05 |
| Device Type | Erasable Programmable Logic Device (EPLD) | Erasable Programmable Logic Device (EPLD) |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM configuration cell |
| Macrocell Count | 48 | — |
| Propagation Delay (tPD) | 22 ns | 35 ns |
| Maximum Supply Voltage | 5.25 V | — |
| I/O Pins | 48 | — |
| Dedicated Inputs | 12 | — |
| Encapsulado | PLCC-68 (QCCJ, J-lead) | 68-pin PLCC (J-Lead, plastic) |
| Terminal Pitch | 1.27 mm | — |
| Terminal Form | J-Bend | — |
| Package Code | QCCJ | — |
| Package Shape | Square | — |
| Operating Temperature Grade | Commercial (0C to 70C) | — |
| Typical Operating Current | 20 mA at 1 MHz | — |
| Maximum Counter Frequency | 50 MHz (4 x 12-bit counters) | — |
| Speed Grade | -20 | 35 (slowest in EP1810L family) |
| Configuration Memory | Non-volatile EPROM (UV-erasable) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Macrocells | — | 48 |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Tensión de alimentación | — | 5 V (TTL-compatible I/O) |
| Temperatura de funcionamiento | — | -40 C to +85 C (industrial, 'I' suffix) |
| Tipo de montaje | — | Surface Mount (PLCC socket compatible) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |