EP1S10B672C6 vs EP1S10B672C7 Comparación
Comparación detallada lado a lado de EP1S10B672C6 por Intel y EP1S10B672C7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S10B672C6 | EP1S10B672C7 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $185,00 | $140,00 |
| Manufacturer | Intel / Altera | Intel (formerly Altera) |
| Series | Stratix | Stratix |
| Logic Elements / Cells | 10,570 | — |
| LABs / CLBs | 1,057 | — |
| User I/Os | 345 | — |
| Encapsulado | 672-BBGA (35 x 35 mm, 1.27 mm pitch) | — |
| Supply Voltage (Core) | 1.5 V (1.425 V - 1.575 V) | 1.5 V |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Maximum Operating Frequency | 450.05 MHz | — |
| Temperatura de funcionamiento | 0 C to 85 C (Commercial Extended) | 0 °C to 85 °C (Commercial) |
| Logic Family | CMOS | CMOS |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Supplier Device Package | 672-BGA | — |
| Memory | Embedded TriMatrix (MRAM/M4K) blocks | — |
| DSP Blocks | Yes, dedicated multiply-accumulate blocks | Yes (DSP multiplier blocks) |
| Clock Management | PLLs for clock synthesis | — |
| Configuration | JTAG / passive serial / fast passive parallel | — |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS compliance] |
| Logic Elements | — | 10,570 |
| Embedded Memory (Total) | — | 920 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| Package Type | — | 672-ball FineLine BGA |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.27 mm |
| Temperature Grade | — | Commercial (C) |
| Speed Grade | — | 7 |
| Configuration Method | — | JTAG / EPC serial configuration |