EP1S20B672C7N vs EP1S20B672C6N Comparación
Comparación detallada lado a lado de EP1S20B672C7N por Intel y EP1S20B672C6N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S20B672C7N | EP1S20B672C6N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $320,00 | $425,00 |
| Series | Stratix | EP1S20 |
| Family | Stratix (original) | Stratix |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Logic Elements (LEs) | 18,460 | — |
| LABs / CLBs | 1,846 | — |
| Embedded Memory Bits | 1,669,248 bits | — |
| Maximum User I/O | 426 | 426 |
| Number of Pins / Balls | 672 | — |
| Package Type | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) | — |
| Supply Voltage (Core, VCCINT) | 1.5 V | — |
| Temperatura de funcionamiento | 0 °C to 85 °C (Commercial Extended) | 0 C to +85 C (Commercial) |
| Speed Grade | -7 | 6 |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Nivel MSL | 3 (per JEDEC J-STD-020) | — |
| Logic Family | CMOS | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements (LE) | — | 18,460 |
| Logic Array Blocks (LAB) | — | 1,846 |
| Embedded Memory | — | 1,669,248 bits |
| Core Voltage | — | 1.5 V |
| Encapsulado | — | 672-ball BGA (672-BBGA), 35 x 35 mm, 1.27 mm pitch |
| Configuration Method | — | Passive Serial / Fast Passive Parallel / JTAG |
| Estado del ciclo de vida | — | Not Recommended for New Designs (NRND) |