EP1S20F672C7N vs EP1S20F672C7 Comparación
Comparación detallada lado a lado de EP1S20F672C7N por Intel y EP1S20F672C7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S20F672C7N | EP1S20F672C7 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $109,20 | $195,00 |
| Series | Stratix (first generation) | Stratix |
| Family | Stratix | Altera Stratix FPGA |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Logic Cells | 18,460 | — |
| Configurable Logic Blocks (CLBs) | 2,132 | — |
| Embedded Memory (TriMatrix) | 1,669,248 bits (426 Kbit total) | — |
| DSP Blocks | 56 (dedicated 18x18 multipliers) | [DATA_NEEDED: DSP block count] |
| Maximum User I/O | 586 | — |
| I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| PLLs | Up to 12 | — |
| Maximum Operating Frequency | 420.17 MHz | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 130 nm CMOS | — |
| Encapsulado | 672-FBGA (FineLine BGA) | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) |
| Package Body Size | 35 mm x 35 mm | — |
| Ball Pitch | 1.27 mm | — |
| Temperatura de funcionamiento | 0°C to +85°C (commercial) | 0C to 85C (commercial) |
| Speed Grade | C7 (-7) | C7 |
| Tipo de montaje | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Yes (lead-free finish, RoHS compliant) | — |
| Configuration Modes | PS, PPS, FPP, JTAG | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| Nivel MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Embedded Memory Bits | — | 1,669,248 |
| User I/O Pins | — | 426 |
| Logic Family | — | CMOS, SRAM-based |
| Core Supply Voltage | — | 1.5 V |
| Estado RoHS | — | unknown |
| Clock PLLs | — | Up to 10 |