EP1S60F1020C7 vs EP1S60F1020C6 Comparación
Comparación detallada lado a lado de EP1S60F1020C7 por Altera y EP1S60F1020C6 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S60F1020C7 | EP1S60F1020C6 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.750,00 | $105,00 |
| Series | Stratix | EP1S60 |
| Family | Stratix (EP1S60) | Stratix |
| Logic Elements | 57,120 | 57,120 |
| Total Memory Bits | 5,215,104 | — |
| Maximum User I/O | 773 | — |
| Encapsulado | 1020-BBGA, FCBGA, 33 x 33 mm, 1.0 mm pitch | 1020-ball FC-FBGA, 33 × 33 mm, 1 mm pitch |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Logic Family | CMOS | — |
| Temperatura de funcionamiento | 0C to +85C (Commercial) | 0 °C to +85 °C (Commercial) |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Speed Grade | 7 | C6 |
| Logic Cells / Logic Blocks | 6,570 (per datasheet Section I nomenclature) | — |
| DSP Blocks | Embedded dedicated multiplier / adder blocks | 12 |
| PLLs | Up to 12 enhanced PLLs per die | — |
| Configuration Method | Serial or parallel with optional decompression | — |
| Nivel MSL | 3 (per BGA moisture-sensitivity norms) | — |
| Estado RoHS | Compliant (lead-free) | [DATA_NEEDED: rohs_status] |
| Logic Array Blocks (LABs) | — | 6,570 |
| Embedded Memory Bits | — | 5,215,104 |
| Maximum User I/O Pins | — | 773 |
| Process Technology | — | 130 nm CMOS |
| Maximum Internal Frequency | — | 450.05 MHz |