EP1SGX10DF672C7N vs EP1SGX25DF67216 Comparación
Comparación detallada lado a lado de EP1SGX10DF672C7N por Intel y EP1SGX25DF67216 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1SGX10DF672C7N | EP1SGX25DF67216 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $198,00 |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Device Family | Stratix GX | — |
| Logic Cells | 10,570 cells | — |
| User I/O | 362 I/O | — |
| Logic Family | CMOS | — |
| Process Technology | 130 nm | — |
| Tensión de alimentación | 1.5 V | — |
| Encapsulado | 672-Ball FC-FBGA | 672-ball FineLine BGA (DF672) |
| Alternative Package Description | FBGA-1020 | — |
| Package Body | 33 mm x 33 mm | — |
| Ball Pitch | 1 mm | — |
| Listed Frequency Figure | 4,385.97 MHz | — |
| Temperatura de funcionamiento | 0 C to 85 C | Industrial, -40C to +100C (I-suffix family) |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| DigiKey Product Category | FPGAs (Field Programmable Gate Array) | — |
| Estado RoHS | unknown | Lead-free / RoHS compliant (per Altera product family documentation) |
| REACH Status | unknown | — |
| AEC-Q100 Status | not_applicable | — |
| Family | — | Stratix GX |
| Logic Elements | — | 25,660 |
| Total RAM Bits | — | 1,944,576 |
| Embedded Multipliers (18x18) | — | [DATA_NEEDED: 18x18 multiplier count] |
| Number of PLLs | — | 4 |
| Number of Transceiver Channels | — | 8 (4 in each of 2 banks) |
| Max Transceiver Data Rate | — | 3.1875 Gbps per channel |
| Min Transceiver Data Rate | — | 500 Mbps |
| Core Supply Voltage | — | 1.5 V |
| Auxiliary Supply Voltage | — | 3.3 V |
| I/O Supply Voltage | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank) |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for DF672 package] |
| On-Die Termination | — | Yes, 100-ohm differential |
| Pre-emphasis / Equalization | — | Programmable (transmitter pre-emphasis; receiver adaptive equalization) |
| Configuration Schemes | — | Passive serial, fast passive parallel, JTAG, Altera enhanced configuration |