EP1SGX10DF672C7N vs EP1SGX25DF67216 비교

다음의 상세 나란히 비교: EP1SGX10DF672C7N 제조: Intel 및 EP1SGX25DF67216 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP1SGX10DF672C7N EP1SGX25DF67216
브랜드 Intel Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 활성 Obsolete
재고 상태 In Stock In Stock
단가 (USD) $0.00 $198.00
Product Type Field Programmable Gate Array (FPGA) —
Device Family Stratix GX —
Logic Cells 10,570 cells —
User I/O 362 I/O —
Logic Family CMOS —
Process Technology 130 nm —
공급 전압 1.5 V —
패키지 672-Ball FC-FBGA 672-ball FineLine BGA (DF672)
Alternative Package Description FBGA-1020 —
Package Body 33 mm x 33 mm —
Ball Pitch 1 mm —
Listed Frequency Figure 4,385.97 MHz —
동작 온도 0 C to 85 C Industrial, -40C to +100C (I-suffix family)
실장 유형 Surface Mount Surface Mount (BGA)
DigiKey Product Category FPGAs (Field Programmable Gate Array) —
RoHS 상태 unknown Lead-free / RoHS compliant (per Altera product family documentation)
REACH Status unknown —
AEC-Q100 Status not_applicable —
Family — Stratix GX
Logic Elements — 25,660
Total RAM Bits — 1,944,576
Embedded Multipliers (18x18) — [DATA_NEEDED: 18x18 multiplier count]
Number of PLLs — 4
Number of Transceiver Channels — 8 (4 in each of 2 banks)
Max Transceiver Data Rate — 3.1875 Gbps per channel
Min Transceiver Data Rate — 500 Mbps
Core Supply Voltage — 1.5 V
Auxiliary Supply Voltage — 3.3 V
I/O Supply Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank)
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for DF672 package]
On-Die Termination — Yes, 100-ohm differential
Pre-emphasis / Equalization — Programmable (transmitter pre-emphasis; receiver adaptive equalization)
Configuration Schemes — Passive serial, fast passive parallel, JTAG, Altera enhanced configuration

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