EP1SGX25DF1020C6B vs EP1SGX25DF1020C6ESL Comparación
Comparación detallada lado a lado de EP1SGX25DF1020C6B por Altera y EP1SGX25DF1020C6ESL por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP1SGX25DF1020C6ESL - Stratix GX FPGA, 25K LE, 1020-BGA | Altera/Intel
EP1SGX25DF1020C6ESL ObsoleteComparación de especificaciones
| Parámetro | EP1SGX25DF1020C6B | EP1SGX25DF1020C6ESL |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $175,00 | $1.095,00 |
| Series | Stratix GX | — |
| Family | EP1SGX25 | Stratix GX |
| Logic Elements | 25,660 | 25,660 |
| Total Memory Bits | 1,944,576 | — |
| User I/O Count | 607 | — |
| Encapsulado | 1020-BBGA (33 × 33 mm, 1.0 mm pitch) | 1020-BBGA (FineLine BGA) |
| Supply Voltage (Core) | 1.5 V | — |
| Temperatura de funcionamiento | 0 °C to 85 °C (Commercial) | — |
| Speed Grade | C6 | C6 |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes (per DigiChip package note) | — |
| Transceivers | Embedded high-speed serial transceivers (multi-gigabit) | Embedded multi-gigabit transceivers (per Stratix GX family) |
| PLLs | On-chip phase-locked loops for clock management | — |
| DSP Blocks | Hardware multipliers / DSP blocks | Yes (embedded DSP blocks) |
| External Memory Support | DDR, DDR2, SDR, QDR, QDRII SRAM | — |
| Hard IP | PCI Express (per Stratix GX family) | — |
| Total RAM Bits | — | 1,944,576 bits |
| User I/O Pins | — | 607 |
| LABs/CLBs | — | 2,566 |
| Core Voltage | — | 1.5 V |
| Temperatura de unión de funcionamiento | — | 0 C to 85 C |
| Configuration Method | — | Passive Serial / Fast Passive Parallel / JTAG |
| Process Node | — | 0.13 um CMOS |
| I/O Standards Supported | — | LVTTL, LVCMOS, SSTL, HSTL, LVDS (per family) |