EP1SGX25DF800C6N vs EP1SGX25DF800C5N Comparación
Comparación detallada lado a lado de EP1SGX25DF800C6N por Intel y EP1SGX25DF800C5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP1SGX25DF800C6N - Stratix GX FPGA, 25K LE, 3.1875 Gbps SERDES | Intel / Altera
EP1SGX25DF800C6N Obsolete
Comparación de especificaciones
| Parámetro | EP1SGX25DF800C6N | EP1SGX25DF800C5N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $118,00 | $158,00 |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 25,560 LEs | — |
| Maximum Transceiver Channels | 20 channels | — |
| Maximum Transceiver Data Rate | 3.1875 Gbps | 3.1875 Gbps per channel |
| Encapsulado | FBGA-780 (FineLine BGA, 800-ball per JEDEC ordering code) | FBGA-800 (FineLine BGA, 31x31 mm) |
| Process Node | [DATA_NEEDED: process node] | — |
| Core Voltage | 1.5 V | — |
| Temperatura de funcionamiento | Commercial (0 C to +85 C) | 0C to +85C (commercial) |
| Speed Grade | 6 | C5 (commercial) |
| Configuration Method | Passive Serial / Passive Parallel / Active Serial / JTAG | — |
| Transceiver Encoding | 8B/10B | — |
| Clock Data Recovery (CDR) | Yes, integrated per channel | — |
| Tipo de memoria | TriMatrix embedded SRAM | — |
| DSP Blocks | Yes, embedded multiplier blocks | Embedded multiplier blocks (family-wide) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Lead Free | [DATA_NEEDED: lead free status] | — |
| Device Logic Elements | — | 25,660 (typical) |
| Transceiver Channels | — | 8 (full-duplex) |
| Process Technology | — | 130 nm |
| Supply Voltage (Core) | — | 1.5 V typical |
| Lead-Free / RoHS Status | — | Lead-free (N suffix) |
| On-Chip Memory (TriMatrix) | — | Approx. 2 Mbits total |
| PLLs | — | Up to 40 (device-wide) |
| Embedded 8b/10b Encoder/Decoder | — | Yes (one per transceiver channel) |
| PCI Express Hard IP | — | x1, x4 endpoints supported |
| Nivel MSL | — | [DATA_NEEDED: MSL Level] |
| Development Software | — | Quartus II (legacy) |