EP1SGX25FF1020C6 vs EP1SGX25FF1020I7 Comparación
Comparación detallada lado a lado de EP1SGX25FF1020C6 por Intel y EP1SGX25FF1020I7 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP1SGX25FF1020C6 - Stratix GX FPGA 25,660 LE 607 I/O FBGA-1020 | Intel
EP1SGX25FF1020C6 ObsoleteAltera
EP1SGX25FF1020I7 - Stratix GX FPGA 25,660 Cells, 1.5V, FC-FBGA-1020 | Altera / Intel
EP1SGX25FF1020I7 ObsoleteComparación de especificaciones
| Parámetro | EP1SGX25FF1020C6 | EP1SGX25FF1020I7 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $135,00 | $210,00 |
| Family | Stratix GX | Stratix GX |
| Series | Stratix GX | EP1SGX25 |
| Logic Family | CMOS | — |
| Logic Elements / Cells | 25,660 | — |
| Number of LABs | 2,566 | — |
| Total Memory Bits | 1,944,576 (1.94 Mbit, TriMatrix) | — |
| User I/O Count | 607 | — |
| Número de pines | 1020 | — |
| Package Type | FBGA-1020 (FC-FBGA) | — |
| Package Dimensions | 33 x 33 mm | — |
| Ball Pitch | 1.0 mm | — |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Temperatura de funcionamiento | 0 °C to 85 °C (Commercial) | — |
| Speed Grade | C6 | 7 (highest production grade) |
| Tipo de montaje | Surface Mount | Surface Mount (FC-FBGA) |
| Estado RoHS | Non-Compliant (legacy Altera era) | [DATA_NEEDED: RoHS compliance] |
| Lead Free | Yes | — |
| Logic Cells | — | 25,660 |
| Configurable Logic Blocks (CLBs) | — | 2,566 |
| Process Technology | — | 130 nm CMOS |
| Encapsulado | — | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) |
| Number of Terminals / Balls | — | 1020 |
| Terminal Form | — | Ball |
| Temperature Grade (suffix 'I') | — | Industrial |
| Terminal Pitch | — | [DATA_NEEDED: terminal pitch] |
| Combinatorial Delay per CLB | — | 9.48 ns (per Microchip USA listing) |
| Combinatorial Delay Variant | — | [DATA_NEEDED: tPD per CLB variant speed grade] |
| Maximum Internal Clock Frequency | — | [DATA_NEEDED: max Fmax in MHz per speed grade] |
| Embedded Transceivers | — | Yes (Stratix GX feature) |
| Configuration Method | — | SRAM-based (volatile, requires configuration at power-up) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |