EP1SGX25FF1020C6 vs EP1SGX25FF1020I7 对比

详细并排对比 EP1SGX25FF1020C6 出自 Intel 和 EP1SGX25FF1020I7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1SGX25FF1020C6 EP1SGX25FF1020I7
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $135.00 $210.00
Family Stratix GX Stratix GX
Series Stratix GX EP1SGX25
Logic Family CMOS —
Logic Elements / Cells 25,660 —
Number of LABs 2,566 —
Total Memory Bits 1,944,576 (1.94 Mbit, TriMatrix) —
User I/O Count 607 —
引脚数 1020 —
Package Type FBGA-1020 (FC-FBGA) —
Package Dimensions 33 x 33 mm —
Ball Pitch 1.0 mm —
Core Supply Voltage 1.5 V 1.5 V
工作温度 0 °C to 85 °C (Commercial) —
Speed Grade C6 7 (highest production grade)
安装类型 Surface Mount Surface Mount (FC-FBGA)
RoHS 状态 Non-Compliant (legacy Altera era) [DATA_NEEDED: RoHS compliance]
Lead Free Yes —
Logic Cells — 25,660
Configurable Logic Blocks (CLBs) — 2,566
Process Technology — 130 nm CMOS
封装 — FC-FBGA-1020 (Flip-Chip Fine-pitch BGA)
Number of Terminals / Balls — 1020
Terminal Form — Ball
Temperature Grade (suffix 'I') — Industrial
Terminal Pitch — [DATA_NEEDED: terminal pitch]
Combinatorial Delay per CLB — 9.48 ns (per Microchip USA listing)
Combinatorial Delay Variant — [DATA_NEEDED: tPD per CLB variant speed grade]
Maximum Internal Clock Frequency — [DATA_NEEDED: max Fmax in MHz per speed grade]
Embedded Transceivers — Yes (Stratix GX feature)
Configuration Method — SRAM-based (volatile, requires configuration at power-up)
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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