EP20K100EQC208-1X vs EP20K100EQC208-3N Comparación
Comparación detallada lado a lado de EP20K100EQC208-1X por Intel y EP20K100EQC208-3N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K100EQC208-1X | EP20K100EQC208-3N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $152,00 | $9,75 |
| Family | APEX-20KE | — |
| Logic Elements | 4,160 | — |
| Typical Gate Count | 100,000 gates | — |
| Embedded Memory (bits) | 53,248 | — |
| Embedded System Blocks (ESBs) | 26 | — |
| Maximum User I/O | 151 | — |
| Encapsulado | 208-pin PQFP (EQC208) | — |
| Process Technology | 0.15 micrometer CMOS, all-layer copper | [DATA_NEEDED: Process technology] |
| Propagation Delay | 1.6 ns | 2.2 ns |
| Speed Grade | -1 (standard) | -3 |
| Temperatura de funcionamiento | 0C to +85C | — |
| Core Supply Voltage | 1.8 V | 1.8 V |
| MultiVolt I/O Support | 1.8V / 2.5V / 3.3V / 5.0V | — |
| PLLs | 4 | — |
| Configuration Interface | JTAG (IEEE 1149.1), passive serial/parallel | — |
| Nivel MSL | 3 (168 Hours) | [DATA_NEEDED: MSL level] |
| Estado RoHS | Lead-free (Pb-free), RoHS compliant | — |
| Product Family | — | APEX-20KE |
| FPGA Type | — | Field Programmable Gate Array |
| Number of Logic Elements | — | 4160 |
| Typical Gates | — | 100000 |
| System Gates | — | 263000 |
| Total RAM Bits | — | 53248 |
| Number of User I/O | — | 151 |
| Frecuencia de reloj máxima | — | 250 MHz |
| Package Type | — | 208-BFQFP (PQFP-208) |
| Tipo de montaje | — | Surface Mount |
| Número de pines | — | 208 |
| Rango de temperatura de funcionamiento | — | 0 °C to +85 °C |
| I/O Standards Supported | — | [DATA_NEEDED: Supported I/O standards] |
| Package Body Dimensions | — | [DATA_NEEDED: Package body dimensions] |
| Terminal Pitch | — | [DATA_NEEDED: Terminal pitch] |