EP20K200EQC208-3 vs EP20K200CF484C8ES Comparación
Comparación detallada lado a lado de EP20K200EQC208-3 por Intel y EP20K200CF484C8ES por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K200EQC208-3 | EP20K200CF484C8ES |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $65,00 | $89,00 |
| Family | APEX 20KE | APEX 20K |
| Series | APEX 20K (enhanced "E" variant) | APEX-20KC |
| Product Type | FPGA (Field Programmable Gate Array), SRAM-based, in-system programmable | — |
| System Gates (typical) | 200,000 | — |
| Logic Elements (LEs) | 8,320 | — |
| Embedded RAM Bits | 106,496 | — |
| Maximum User I/O | 136 | — |
| Speed Grade | -3 | C8 (-8 commercial) |
| Core Supply Voltage (VCCINT) | 2.5 V (typical, APEX 20KE generation) | — |
| I/O Supply Voltage (VCCIO) | MultiVolt, 1.8 V / 2.5 V / 3.3 V / 5 V compatible | — |
| Encapsulado | 208-BFQFP / PQFP208 (Plastic Quad Flat Pack, gull-wing) | 484-pin FBGA (FineLine BGA) |
| Terminal Pitch | 0.5 mm | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Technology | CMOS, SRAM configuration cell | — |
| Configuration Mode | Fast Passive Parallel (FPP), Passive Serial (PS), JTAG (IEEE 1149.1) | — |
| Embedded Array Blocks (EABs) | Yes (dual-port RAM/ROM, up to 16-bit wide) | — |
| MultiVolt I/O Support | Yes | — |
| LVDS Support | True-LVDS (enhanced "E" variant feature) | — |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 Hours) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Operating Temperature (Commercial) | 0 °C to 85 °C | — |
| Logic Elements | — | 8,320 |
| System Gates | — | 200,000 |
| Embedded Memory (RAM bits) | — | 106,496 |
| Number of Logic Array Blocks (LABs) | — | 104 |
| Number of Embedded System Blocks (ESBs) | — | 13 |
| User I/O Pins (max) | — | 376 |
| PLLs | — | 4 |
| Core Voltage | — | 1.8 V |
| Temperatura de funcionamiento | — | 0C to +85C (commercial) |
| Process Node | — | 0.18 micron CMOS |
| Configuration Interface | — | JTAG (IEEE 1149.1) / Altera serial |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL, SSTL, HSTL, AGP |
| Lead Free / RoHS | — | [DATA_NEEDED: lead-free status] |