EP20K200EQC240-3N vs EP20K300EQC240-3 Comparación
Comparación detallada lado a lado de EP20K200EQC240-3N por Altera y EP20K300EQC240-3 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K200EQC240-3N | EP20K300EQC240-3 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $45,25 | $87,20 |
| Series | APEX-20KE | — |
| Number of Logic Elements/Cells | 8320 | — |
| Number of Gates | 200000 | — |
| Total RAM Bits | 106496 bits | — |
| Number of User I/Os | 168 | — |
| Voltage - Supply | 1.71V ~ 1.89V | — |
| Core Supply Voltage | 1.8 V nominal | — |
| Maximum Internal Frequency | 189 MHz common -3 speed listing | — |
| Speed Grade | -3 | -3 |
| Temperatura de funcionamiento | 0 to 85 C | 0C to +85C (commercial) |
| Encapsulado / Carcasa | 240-BQFP | — |
| Supplier Device Package | 240-PQFP (32x32) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Technology | CMOS | — |
| Process Technology | 0.22 um | 0.22 um CMOS |
| Configuration Type | SRAM-based, external configuration required | — |
| Estado del ciclo de vida | Obsolete / legacy distribution via Rochester Electronics | — |
| I/O Standards Supported | [DATA_NEEDED: I/O standards from APEX-20KE datasheet] | — |
| Configuration Bitstream Size | [DATA_NEEDED: exact configuration file size for EP20K200E] | — |
| Thermal Resistance (theta_JA) | [DATA_NEEDED: thermal resistance for 240-BQFP] | — |
| Estado RoHS | Unknown; N suffix often indicates Pb-free finish but not confirmed in verified snippets | [DATA_NEEDED: confirm for this date code] |
| Family | — | APEX-20KE |
| Typical Gates | — | 300,000 |
| Logic Elements / Cells | — | 11,520 |
| Embedded Memory (bits) | — | 147,456 |
| Maximum User I/O | — | 152 |
| Number of PLLs | — | 4 |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage Tolerance | — | 2.5V / 3.3V / 5.0V compatible |
| Encapsulado | — | 240-pin PQFP / BFQFP (240-BFQFP) |
| Pin Pitch | — | 1.0 mm |
| Terminal Form | — | Gull Wing |
| Programmable Logic Type | — | Loadable PLD |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Configuration Interface | — | JTAG (IEEE 1149.1), passive serial |