EP20K400CB652I7 vs EP20K400CB652C9N Comparación
Comparación detallada lado a lado de EP20K400CB652I7 por Altera y EP20K400CB652C9N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400CB652I7 | EP20K400CB652C9N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $149,50 | $195,00 |
| Family | APEX 20KC | APEX 20KC |
| Device Family | Field-Programmable Gate Array (FPGA) | — |
| Typical Gates | 400,000 | — |
| Logic Elements (LEs) | 16,640 | — |
| Maximum Operating Frequency | 375.94 MHz | — |
| Process Technology | 0.15 µm CMOS | — |
| Core Supply Voltage | 1.8 V | — |
| I/O Supply Voltage | 1.8 V / 3.3 V | — |
| Encapsulado | BGA-652 (652-ball) | BGA-652 (Plastic Ball Grid Array, 652 balls) |
| Package Code (JESD-30) | S-PBGA-B652 | — |
| Terminal Form | Ball | — |
| Package Shape | Square | — |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O] | — |
| Embedded Memory | Embedded System Blocks (ESB) - dual-port RAM / FIFO / CAM | — |
| Configuration Method | SRAM + JTAG (ISP) | — |
| Speed Grade | 7 | — |
| Temperature Grade | Industrial (-40 °C to +100 °C) | — |
| Estado RoHS | Non-compliant (JESD-609 e0, contains lead) | Unknown (legacy Altera part - verify with distributor) |
| Manufacturer Status | Obsolete (Intel/Altera legacy FPGA) | — |
| Series | — | EP20K400 |
| Device Type | — | Programmable Logic Device (SOPC FPGA) |
| Architecture | — | MultiCore (LUT logic + Embedded System Blocks) |
| System Gates | — | 400,000 |
| Logic Elements | — | 16,640 |
| Maximum User I/Os | — | 502 |
| Total Memory Bits | — | 212,992 (per chip) |
| Maximum Internal Frequency | — | 250 MHz |
| Propagation Delay | — | 2.0 ns |
| Logic Family | — | CMOS |
| Core Process Technology | — | 0.15 µm all-layer copper CMOS |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V |
| Rango de temperatura de funcionamiento | — | 0 °C to +85 °C (Commercial) |
| Tipo de montaje | — | Surface Mount |
| Configuration Interface | — | IEEE 1149.1 JTAG, serial passive parallel async |