EP20K400CF672C7 vs EP20K400CF672C-8 Comparación
Comparación detallada lado a lado de EP20K400CF672C7 por Altera y EP20K400CF672C-8 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400CF672C7 | EP20K400CF672C-8 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,00 | $95,00 |
| Series | APEX-20KC | — |
| Family | APEX 20KC (MultiCore™) | APEX 20K |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | — |
| Embedded Memory (RAM bits) | 212,992 | — |
| Maximum User I/O | 488 | 488 |
| Number of I/O Banks | 8 | [DATA_NEEDED: number of I/O banks] |
| Encapsulado | 672-BBGA (FC-FBGA, FineLine BGA) | — |
| Recuento de pines | 672 | — |
| Core Voltage | 1.8 V | — |
| Tensión de alimentación | 2.5 V (I/O reference) | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper CMOS |
| Propagation Delay (tPD) | 2.5 ns | — |
| Maximum Internal Frequency | 375.94 MHz | — |
| Temperatura de funcionamiento | 0 °C to +85 °C (Commercial, C-grade) | — |
| PLL Count | 4 | — |
| Speed Grade | -7 | -8 |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Estado RoHS | Non-compliant (legacy product) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Contains lead (legacy BGA finish) | — |
| Logic Elements | — | 16,640 |
| Typical Gates | — | 400,000 |
| Macros | — | 1,664 |
| Package Type | — | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | — | 1.78 ns (speed grade -8) |
| Temperature Grade (C) | — | Commercial, 0 °C to 85 °C |
| Embedded Memory Type | — | ESB (RAM / ROM / CAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |