EP20K400CF672C7 vs EP20K400CF672C-8 对比

详细并排对比 EP20K400CF672C7 出自 Altera 和 EP20K400CF672C-8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400CF672C7 EP20K400CF672C-8
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $95.00
Series APEX-20KC —
Family APEX 20KC (MultiCore™) APEX 20K
Logic Elements / Cells 16,640 —
System Gates 400,000 —
Embedded Memory (RAM bits) 212,992 —
Maximum User I/O 488 488
Number of I/O Banks 8 [DATA_NEEDED: number of I/O banks]
封装 672-BBGA (FC-FBGA, FineLine BGA) —
引脚数量 672 —
Core Voltage 1.8 V —
电源电压 2.5 V (I/O reference) —
Process Technology 0.15 µm CMOS 0.15 µm all-layer copper CMOS
Propagation Delay (tPD) 2.5 ns —
Maximum Internal Frequency 375.94 MHz —
工作温度 0 °C to +85 °C (Commercial, C-grade) —
PLL Count 4 —
Speed Grade -7 -8
安装类型 Surface Mount (BGA) Surface Mount (BGA)
RoHS 状态 Non-compliant (legacy product) [DATA_NEEDED: RoHS compliance]
Lead-Free Contains lead (legacy BGA finish) —
Logic Elements — 16,640
Typical Gates — 400,000
Macros — 1,664
Package Type — PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch)
Core Voltage (VCCINT) — 1.8 V nominal (1.71 V to 1.89 V)
I/O Voltage (VCCIO) — [DATA_NEEDED: VCCIO options]
Pin-to-Pin Delay (tPD) — 1.78 ns (speed grade -8)
Temperature Grade (C) — Commercial, 0 °C to 85 °C
Embedded Memory Type — ESB (RAM / ROM / CAM)
Configuration Interface — JTAG (IEEE 1149.1), Passive Serial, Passive Parallel
JTAG Support — Yes (IEEE 1149.1 boundary-scan)
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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