EP20K400CF672C9 vs EP20K400CF672I7 Comparación
Comparación detallada lado a lado de EP20K400CF672C9 por Altera y EP20K400CF672I7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K400CF672C9 - APEX-20K 400K Gates FPGA, 672-FBGA | Intel / Altera
EP20K400CF672C9 Obsolete
Comparación de especificaciones
| Parámetro | EP20K400CF672C9 | EP20K400CF672I7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $390,40 | $190,50 |
| Series | APEX-20KC | — |
| Logic Family / Architecture | MultiCore (LUT + ESB) | — |
| System Gates | 400,000 | — |
| Logic Cells / Elements | 16,640 | — |
| Maximum User I/Os | 488 | — |
| Encapsulado / Carcasa | 672-BBGA, FCBGA | — |
| Supplier Device Package | 672-FBGA (27x27 mm) | — |
| Ball Pitch | 1.0 mm | — |
| Core Supply Voltage | 2.5 V | 1.8 V |
| I/O Supply Voltage | [DATA_NEEDED: I/O VCCIO range] | 1.8 V / 3.3 V |
| Process Technology | 0.22 um CMOS | 0.15 um CMOS |
| Internal Maximum Frequency | 368 MHz | — |
| Propagation Delay | 2.5 ns | — |
| Temperatura de funcionamiento | 0C to +85C (Commercial) | -40 C to +85 C (industrial) |
| Embedded Memory | Embedded System Blocks (ESB) | — |
| Configuration Method | Serial / Parallel PROM | — |
| Estado RoHS | RoHS non-compliant (legacy) | — |
| Tipo de montaje | Surface Mount | — |
| Family | — | APEX 20KC |
| Logic Elements | — | 16,640 |
| Maximum System Gates | — | 400,000 |
| Embedded Memory (ESB) | — | 212,992 bits |
| Maximum User I/O Pins | — | [DATA_NEEDED: pin count for CF672 package] |
| PLL Count | — | 4 |
| Speed Grade | — | I7 |
| Encapsulado | — | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Terminal Finish | — | Tin/Lead (Sn/Pb) |
| JESD-609 Code | — | e0 |
| Nivel de sensibilidad a la humedad (MSL) | — | 3 |
| Configuration Mode | — | PS / AS / JTAG (IEEE 1149.1) |