EP20K400FC672-3 vs EP20K400FI672-3 Comparación
Comparación detallada lado a lado de EP20K400FC672-3 por Altera y EP20K400FI672-3 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400FC672-3 | EP20K400FI672-3 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $138,00 | $195,00 |
| Family | APEX 20K | APEX 20K |
| Device Logic Elements | 16,640 cells | — |
| Typical Gate Count | 400,000 system gates | — |
| Maximum User I/Os | 502 | — |
| Propagation Delay | 2.5 ns | 3.6 ns |
| Internal Performance | 167 MHz | — |
| Process Technology | 0.22 µm CMOS | CMOS |
| Core Supply Voltage | 2.5 V | — |
| Logic Family | CMOS, SRAM-based | — |
| Encapsulado | 672-pin FC-FBGA | — |
| Package Code | BGA | S-PBGA-B672 |
| Number of Terminals | 672 | — |
| Terminal Form | Ball (BGA) | — |
| Speed Grade | -3 (commercial fastest) | — |
| Temperatura de funcionamiento | 0 °C to 85 °C | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount | Surface Mount |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming Method | SRAM, JTAG (ByteBlaster) | — |
| Estado del ciclo de vida | Obsolete / Legacy | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Series | — | EP20K400 |
| Logic Elements | — | 16640 |
| Total Gates | — | up to 400000 |
| Embedded RAM | — | 212992 bits |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Frecuencia de reloj máxima | — | 833 MHz |
| Supply Voltage (Nominal) | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| Package Type | — | PBGA (Plastic BGA) |
| Terminal Count | — | 672 |
| Terminal Pitch | — | 1.000 mm |
| Package Shape | — | Square BGA |
| Configuration Interface | — | JTAG (IEEE 1149.1) |
| Nivel MSL | — | 3 |
| Peak Reflow Temperature | — | 220 C |