EP20K400FI672-2 vs EP20K400FI672-2N Comparación
Comparación detallada lado a lado de EP20K400FI672-2 por Altera y EP20K400FI672-2N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 ObsoleteComparación de especificaciones
| Parámetro | EP20K400FI672-2 | EP20K400FI672-2N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $92,40 | $188,75 |
| Family | APEX-20K | APEX 20K |
| Logic Elements | 16640 | — |
| Maximum Gates | 400,000 gates | — |
| User I/Os | 502 | — |
| Embedded Memory Bits | 212992 | 212,992 bits |
| Number of Macros | 1664 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | — |
| Maximum Internal Frequency | 200 MHz | — |
| Propagation Delay | 2.5 ns | 3.1 ns |
| Temperatura de funcionamiento | 0 °C to +85 °C (Commercial) | Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] |
| Package Type | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) | — |
| PLLs (Phase-Locked Loops) | 4 | — |
| Configuration Modes | JTAG, Passive Serial, Passive Parallel | PS, PPS, PPA, JTAG |
| Estado RoHS | Lead-free / RoHS Compliant | Compliant (lead-free) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Typical Gates | — | 400,000 |
| Logic Elements / Cells | — | 16,640 |
| Maximum User I/O | — | 488 |
| Embedded Array Blocks (EABs) | — | [DATA_NEEDED: EAB count per family datasheet] |
| Core Voltage | — | 2.5 V |
| Maximum Frequency | — | 200 MHz |
| Encapsulado | — | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Package Body Size | — | 27 x 27 mm |
| Terminal Pitch | — | 1.0 mm |
| Speed Grade | — | -2 |
| Nivel de sensibilidad a la humedad (MSL) | — | 3 |
| Peak Reflow Temperature | — | 220 °C |
| Supported I/O Standards | — | LVTTL, LVCMOS, SSTL, HSTL |