EP20K400FI672-2 vs EP20K400FI672-2N Comparaison
Comparaison détaillée côte à côte de EP20K400FI672-2 par Altera et EP20K400FI672-2N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 ObsoleteComparaison des spécifications
| Paramètre | EP20K400FI672-2 | EP20K400FI672-2N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $92,40 | $188,75 |
| Family | APEX-20K | APEX 20K |
| Logic Elements | 16640 | — |
| Maximum Gates | 400,000 gates | — |
| User I/Os | 502 | — |
| Embedded Memory Bits | 212992 | 212,992 bits |
| Number of Macros | 1664 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | — |
| Maximum Internal Frequency | 200 MHz | — |
| Propagation Delay | 2.5 ns | 3.1 ns |
| Température de fonctionnement | 0 °C to +85 °C (Commercial) | Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] |
| Package Type | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) | — |
| PLLs (Phase-Locked Loops) | 4 | — |
| Configuration Modes | JTAG, Passive Serial, Passive Parallel | PS, PPS, PPA, JTAG |
| Statut RoHS | Lead-free / RoHS Compliant | Compliant (lead-free) |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Typical Gates | — | 400,000 |
| Logic Elements / Cells | — | 16,640 |
| Maximum User I/O | — | 488 |
| Embedded Array Blocks (EABs) | — | [DATA_NEEDED: EAB count per family datasheet] |
| Core Voltage | — | 2.5 V |
| Maximum Frequency | — | 200 MHz |
| Boîtier | — | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Package Body Size | — | 27 x 27 mm |
| Terminal Pitch | — | 1.0 mm |
| Speed Grade | — | -2 |
| Niveau de sensibilité à l'humidité (MSL) | — | 3 |
| Peak Reflow Temperature | — | 220 °C |
| Supported I/O Standards | — | LVTTL, LVCMOS, SSTL, HSTL |