EP20K400FI672-3V vs EP20K400FI672-3 Comparación
Comparación detallada lado a lado de EP20K400FI672-3V por Intel y EP20K400FI672-3 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400FI672-3V | EP20K400FI672-3 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $285,00 | $195,00 |
| Family | APEX 20K (EP20K400) | APEX 20K |
| Logic Elements | 16,640 | 16640 |
| Maximum Gates | 400,000 | — |
| Typical Gates | [DATA_NEEDED: typical gates value] | — |
| Embedded Memory (bits) | 212,992 | — |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 6 | 6 |
| Total User I/O + Dedicated Inputs | 496 + 6 (variant dependent) | — |
| Frecuencia de reloj máxima | 714.2 MHz | 833 MHz |
| Speed Grade | -3 (faster) | — |
| Core Voltage (VCCINT) | 2.5 V nominal (2.375 V to 2.625 V) | — |
| Process Technology | 0.18 µm CMOS, 4 metal layers | CMOS |
| Encapsulado | 672-ball FineLine BGA (BBGA), 1.0 mm pitch | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programmable via JTAG | Yes (IEEE 1149.1) | — |
| Supported I/O Standards | LVCMOS, LVTTL, SSTL, GTL+, HSTL | — |
| Configuration Modes | JTAG, passive serial, passive parallel | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Temperatura de funcionamiento | -40 °C to +85 °C (industrial) | [DATA_NEEDED: operating temperature range] |
| Nivel MSL | [DATA_NEEDED: MSL rating] | 3 |
| Series | — | EP20K400 |
| Total Gates | — | up to 400000 |
| Embedded RAM | — | 212992 bits |
| Propagation Delay | — | 3.6 ns |
| Supply Voltage (Nominal) | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| Package Type | — | PBGA (Plastic BGA) |
| Package Code | — | S-PBGA-B672 |
| Terminal Count | — | 672 |
| Terminal Pitch | — | 1.000 mm |
| Package Shape | — | Square BGA |
| Configuration Interface | — | JTAG (IEEE 1149.1) |
| Peak Reflow Temperature | — | 220 C |