EP20K400GC652-1XV vs EP20K400GC655-1 Comparación
Comparación detallada lado a lado de EP20K400GC652-1XV por Altera y EP20K400GC655-1 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteComparación de especificaciones
| Parámetro | EP20K400GC652-1XV | EP20K400GC655-1 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $190,00 | $135,00 |
| Family | APEX 20K | APEX 20K |
| Logic Elements (Macros) | 1664 | — |
| Typical System Gates | 400,000 | — |
| Maximum User I/O | 502 | 502 |
| Embedded SRAM | 212,992 bits | — |
| Core Supply Voltage | 2.5 V | 2.5 V |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Logic Family | CMOS | — |
| Package Type | BGA-652 (thermally enhanced) | — |
| Temperatura de funcionamiento | 0 C to +85 C | 0 °C to +85 °C (commercial) |
| Speed Grade | -1 (standard) | — |
| Tipo de montaje | Surface Mount | Through-Hole |
| Estado RoHS | Compliant (lead-free, V suffix) | Non-compliant (contains lead in ceramic package) |
| Architecture | MultiCore (LUT + EAB + FastTrack interconnect) | — |
| Programming Interface | JTAG (IEEE 1149.1) / passive serial | — |
| Series | — | EP20K400 |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Total RAM Bits | — | 212,992 |
| Dedicated Inputs | — | 6 |
| Process Technology | — | 0.22 µm CMOS |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 250 MHz |
| Encapsulado | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Recuento de pines | — | 655 |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |