EP20K400GC655-2 vs EP20K400GC655-1 Comparación
Comparación detallada lado a lado de EP20K400GC655-2 por Altera y EP20K400GC655-1 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteComparación de especificaciones
| Parámetro | EP20K400GC655-2 | EP20K400GC655-1 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $80,00 | $135,00 |
| Series | APEX-20KC | EP20K400 |
| Family | APEX 20K | APEX 20K |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| System Gates | 400,000 | — |
| Logic Cells / Elements | 16,640 | — |
| Total RAM Bits | 212,992 | 212,992 |
| Maximum Internal Frequency | 200 MHz | 250 MHz |
| Speed Grade | -2 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 1.71 V to 1.89 V (MultiVolt) | 3.3 V |
| LVDS Support | Yes | — |
| PLLs | 4 | — |
| Recuento de pines | 655 | 655 |
| Package Type | 655-BCPGA (CPGA-655) | — |
| Package Dimensions | 62.48 x 62.48 mm | — |
| Tipo de montaje | Through-Hole (CPGA) | Through-Hole |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (contains lead in ceramic package) |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Propagation Delay | — | 2.5 ns |
| Encapsulado | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |