EP20K400GC655-2 vs EP20K400GC655-1 Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-2 par Altera et EP20K400GC655-1 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteComparaison des spécifications
| Paramètre | EP20K400GC655-2 | EP20K400GC655-1 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $80,00 | $135,00 |
| Series | APEX-20KC | EP20K400 |
| Family | APEX 20K | APEX 20K |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| System Gates | 400,000 | — |
| Logic Cells / Elements | 16,640 | — |
| Total RAM Bits | 212,992 | 212,992 |
| Maximum Internal Frequency | 200 MHz | 250 MHz |
| Speed Grade | -2 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 1.71 V to 1.89 V (MultiVolt) | 3.3 V |
| LVDS Support | Yes | — |
| PLLs | 4 | — |
| Nombre de broches | 655 | 655 |
| Package Type | 655-BCPGA (CPGA-655) | — |
| Package Dimensions | 62.48 x 62.48 mm | — |
| Type de montage | Through-Hole (CPGA) | Through-Hole |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (contains lead in ceramic package) |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Propagation Delay | — | 2.5 ns |
| Boîtier | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |