EP20K400GC655-2V vs EP20K400GC655-3 Comparación
Comparación detallada lado a lado de EP20K400GC655-2V por Altera y EP20K400GC655-3 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Última compraComparación de especificaciones
| Parámetro | EP20K400GC655-2V | EP20K400GC655-3 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $92,75 | $310,00 |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20KC (1.8 V, LVDS) | APEX 20K |
| Logic Elements | 16,640 | 16640 |
| Total RAM Bits | 212,992 | 212992 |
| System Gates | ~400,000 (typical marketing figure) | — |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 3.000 ns | — |
| Process Technology | CMOS, 0.18 um | 0.22 um CMOS |
| LVDS Support | Yes | — |
| Encapsulado | 655-CPGA (62.48 x 62.48 mm) | — |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| Tipo de montaje | Through-hole (CPGA) | — |
| Speed Grade | -2 | -3 (slowest grade in family) |
| Temperatura de funcionamiento | [DATA_NEEDED: temperature grade] | -40C to +85C (industrial) |
| Estado RoHS | unknown | [DATA_NEEDED: rohs status] |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Manufacturer | — | Intel (formerly Altera) |
| Number of Gates | — | 400000 |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Voltage Tolerance | — | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | — | 167 MHz (per FPGAkey) |
| Encapsulado / Carcasa | — | 655-BCPGA |
| Supplier Device Package | — | 655-CPGA (62.48 x 62.48 mm) |
| Propagation Delay (tPD) | — | 3.6 ns (per Microchip USA listing) |
| JTAG Support | — | IEEE 1149.1 Boundary-Scan |
| Configuration Modes | — | Passive Serial, Passive Parallel Sync/Async, Active Serial |