EP20K400GC655-2V vs EP20K400GC655-3 Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-2V par Altera et EP20K400GC655-3 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP20K400GC655-2V | EP20K400GC655-3 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $92,75 | $310,00 |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20KC (1.8 V, LVDS) | APEX 20K |
| Logic Elements | 16,640 | 16640 |
| Total RAM Bits | 212,992 | 212992 |
| System Gates | ~400,000 (typical marketing figure) | — |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 3.000 ns | — |
| Process Technology | CMOS, 0.18 um | 0.22 um CMOS |
| LVDS Support | Yes | — |
| Boîtier | 655-CPGA (62.48 x 62.48 mm) | — |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| Type de montage | Through-hole (CPGA) | — |
| Speed Grade | -2 | -3 (slowest grade in family) |
| Température de fonctionnement | [DATA_NEEDED: temperature grade] | -40C to +85C (industrial) |
| Statut RoHS | unknown | [DATA_NEEDED: rohs status] |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Manufacturer | — | Intel (formerly Altera) |
| Number of Gates | — | 400000 |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Voltage Tolerance | — | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | — | 167 MHz (per FPGAkey) |
| Boîtier / Format | — | 655-BCPGA |
| Supplier Device Package | — | 655-CPGA (62.48 x 62.48 mm) |
| Propagation Delay (tPD) | — | 3.6 ns (per Microchip USA listing) |
| JTAG Support | — | IEEE 1149.1 Boundary-Scan |
| Configuration Modes | — | Passive Serial, Passive Parallel Sync/Async, Active Serial |