EP20K400GI655-2 vs EP20K400GI655-1 Comparación
Comparación detallada lado a lado de EP20K400GI655-2 por Altera y EP20K400GI655-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400GI655-2 | EP20K400GI655-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $175,00 | $195,00 |
| Manufacturer | Altera Corporation | — |
| Series | APEX 20K (EP20K400) | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Typical Gate Count | 400,000 gates | — |
| Logic Elements (LE) | 16,640 | — |
| Maximum User I/O | 496 | 502 |
| Dedicated Inputs | 6 | 4 |
| Number of Terminals | 655 | — |
| Encapsulado | SPGA-655 (47 mm x 47 mm) | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Propagation Delay | 3.1 ns (typical) | 2.5 ns |
| Technology | CMOS SRAM | CMOS, SRAM-based |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Tipo de montaje | Through-Hole / Socket | — |
| Moisture Sensitivity Level | 1 (per Altera family) | MSL 1 |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | — |
| Embedded Memory | Embedded System Blocks (ESBs) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Estado del ciclo de vida | Obsolete (legacy Altera APEX 20K family) | — |
| Family | — | APEX 20K |
| Device Series | — | EP20K400 |
| Logic Elements | — | 16640 |
| Typical Gates | — | 400000 |
| Total Terminals | — | 655 |
| Package Type | — | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | — | S-CPGA-P655 |
| Peak Reflow Temperature | — | 220 C |
| Programmability | — | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | — | 0.18 micrometer CMOS |