EP20K400GI655-2 vs EP20K400GI655-1 对比
详细并排对比 EP20K400GI655-2 出自 Altera 和 EP20K400GI655-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K400GI655-2 | EP20K400GI655-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $175.00 | $195.00 |
| Manufacturer | Altera Corporation | — |
| Series | APEX 20K (EP20K400) | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Typical Gate Count | 400,000 gates | — |
| Logic Elements (LE) | 16,640 | — |
| Maximum User I/O | 496 | 502 |
| Dedicated Inputs | 6 | 4 |
| Number of Terminals | 655 | — |
| 封装 | SPGA-655 (47 mm x 47 mm) | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Propagation Delay | 3.1 ns (typical) | 2.5 ns |
| Technology | CMOS SRAM | CMOS, SRAM-based |
| 工作温度 | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| 安装类型 | Through-Hole / Socket | — |
| Moisture Sensitivity Level | 1 (per Altera family) | MSL 1 |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | — |
| Embedded Memory | Embedded System Blocks (ESBs) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | Compliant |
| 生命周期状态 | Obsolete (legacy Altera APEX 20K family) | — |
| Family | — | APEX 20K |
| Device Series | — | EP20K400 |
| Logic Elements | — | 16640 |
| Typical Gates | — | 400000 |
| Total Terminals | — | 655 |
| Package Type | — | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | — | S-CPGA-P655 |
| Peak Reflow Temperature | — | 220 C |
| Programmability | — | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | — | 0.18 micrometer CMOS |