EP20K400GI655-2 vs EP20K400GI655-1X Comparación
Comparación detallada lado a lado de EP20K400GI655-2 por Altera y EP20K400GI655-1X por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X ObsoleteComparación de especificaciones
| Parámetro | EP20K400GI655-2 | EP20K400GI655-1X |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $175,00 | $160,00 |
| Manufacturer | Altera Corporation | — |
| Series | APEX 20K (EP20K400) | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Typical Gate Count | 400,000 gates | — |
| Logic Elements (LE) | 16,640 | — |
| Maximum User I/O | 496 | — |
| Dedicated Inputs | 6 | 4 |
| Number of Terminals | 655 | 655 |
| Encapsulado | SPGA-655 (47 mm x 47 mm) | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Propagation Delay | 3.1 ns (typical) | 2.5 ns (typical for -1 grade) |
| Technology | CMOS SRAM | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40 C to +85 C (industrial) |
| Tipo de montaje | Through-Hole / Socket | Through-Hole (PGA) |
| Moisture Sensitivity Level | 1 (per Altera family) | — |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | — |
| Embedded Memory | Embedded System Blocks (ESBs) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Estado del ciclo de vida | Obsolete (legacy Altera APEX 20K family) | — |
| Family | — | APEX 20K |
| Device | — | EP20K400 |
| Logic Elements | — | 16640 |
| User I/O Lines | — | 502 |
| Package Type | — | Ceramic Pin Grid Array (CPGA) |
| Package Code (JESD-30) | — | S-CPGA-P655 |
| Package Equivalence Code | — | SPGA655,47X47 |
| Package Body Material | — | CERAMIC (metal-sealed co-fired) |
| Speed Grade | — | -1 |
| Process Technology | — | CMOS, SRAM-based configuration |
| Nivel de sensibilidad a la humedad (MSL) | — | 1 |
| Peak Reflow Temperature | — | 220 C |