EP20K600CF33C8N vs EP20K600CF33C9 Comparación
Comparación detallada lado a lado de EP20K600CF33C8N por Intel y EP20K600CF33C9 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K600CF33C8N | EP20K600CF33C9 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $162,75 | $171,00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements / Cells | 24,320 | 24,320 |
| Total RAM Bits | 311,296 | — |
| Number of LABs / CLBs | 2,432 | — |
| Number of Gates | 1,537,000 (max) | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Core Voltage Supply | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Technology / Process | 0.15 µm CMOS | — |
| Maximum Internal Frequency | 301.21 MHz | — |
| Speed Grade | -8 (slower than -7) | — |
| Temperatura de funcionamiento | 0°C to 85°C (TJ) | — |
| Encapsulado | 1020-pin FC-FBGA (flip-chip) | 1020-ball FC-FBGA |
| Pitch | 0.33 mm | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Programmable Type | In-System / SRAM-based | — |
| Configuration Interface | JTAG (IEEE 1149.1) + Passive Serial / Parallel | — |
| Estado RoHS | Compliant (N suffix) | [DATA_NEEDED: rohs status] |
| Process Technology | — | 0.15 µm CMOS |
| System Gates | — | 600,000 (maximum) |
| Maximum Operating Frequency | — | 250 MHz |
| Frecuencia de reloj máxima | — | 303.03 MHz |
| Propagation Delay | — | 2.0 ns |
| Core Supply Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| User I/O | — | 588 (4 dedicated inputs + 580 general-purpose I/O) |
| Rango de temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Embedded RAM | — | Dual-port RAM blocks (per family) |
| Programmability | — | JTAG / IEEE 1149.1 ISP, SRAM-based |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |
| Logic Block Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS (per family datasheet) |