EP20K600CF33C8N vs EP20K600CF33C9 对比

详细并排对比 EP20K600CF33C8N 出自 Intel 和 EP20K600CF33C9 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600CF33C8N EP20K600CF33C9
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $162.75 $171.00
Family APEX 20KC APEX 20KC
Logic Elements / Cells 24,320 24,320
Total RAM Bits 311,296 —
Number of LABs / CLBs 2,432 —
Number of Gates 1,537,000 (max) —
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Core Voltage Supply 1.71 V to 1.89 V (1.8 V nominal) —
Technology / Process 0.15 µm CMOS —
Maximum Internal Frequency 301.21 MHz —
Speed Grade -8 (slower than -7) —
工作温度 0°C to 85°C (TJ) —
封装 1020-pin FC-FBGA (flip-chip) 1020-ball FC-FBGA
Pitch 0.33 mm —
安装类型 Surface Mount Surface Mount (BGA)
Programmable Type In-System / SRAM-based —
Configuration Interface JTAG (IEEE 1149.1) + Passive Serial / Parallel —
RoHS 状态 Compliant (N suffix) [DATA_NEEDED: rohs status]
Process Technology — 0.15 µm CMOS
System Gates — 600,000 (maximum)
Maximum Operating Frequency — 250 MHz
最大时钟频率 — 303.03 MHz
Propagation Delay — 2.0 ns
Core Supply Voltage (VCCINT) — 1.8 V nominal (1.71 V to 1.89 V)
User I/O — 588 (4 dedicated inputs + 580 general-purpose I/O)
工作温度范围 — [DATA_NEEDED: operating temperature range]
Embedded RAM — Dual-port RAM blocks (per family)
Programmability — JTAG / IEEE 1149.1 ISP, SRAM-based
MSL 等级 — [DATA_NEEDED: MSL level]
Logic Block Architecture — MultiCore (LUT + product-term + embedded memory)
I/O Standards Supported — LVTTL, LVCMOS, LVDS (per family datasheet)

数据手册与资源

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