EP20K600CF672-3 vs EP20K600CEF672C7 Comparación
Comparación detallada lado a lado de EP20K600CF672-3 por Intel y EP20K600CEF672C7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K600CF672-3 | EP20K600CEF672C7 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $99,50 | $98,40 |
| Family | APEX 20KC | APEX 20KC (Enhanced Configuration) |
| Typical Gates | 600,000 | — |
| Maximum System Gates | 2,432,000 | — |
| Maximum Logic Elements | 2,432 | — |
| Embedded System Memory | 311,040 bits (380 Kbits ESB) | — |
| User I/O Pins | 488 | — |
| Encapsulado | 672-ball FineLine BGA | 672-ball FineLine BGA (FC-FBGA) |
| Speed Grade | -3 | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm CMOS, all-layer copper |
| PLLs | 4 | — |
| Maximum Internal Frequency | 180 MHz (per APEX 20K family datasheet) | — |
| Configuration Modes | PS, PPS, PPA, JTAG, EPC2/EPC16 | — |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL-2/3, HSTL, LVDS, PCI | — |
| Tipo de montaje | Surface Mount | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (commercial) |
| Estado RoHS | Lead-free / RoHS compliant (per Alibaba listing) | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | APEX 20KC |
| Device Type | — | FPGA / Loadable PLD |
| Logic Elements / Cells | — | 24,320 |
| Gate Count (typical) | — | 600,000 gates |
| Maximum Operating Frequency | — | 375.94 MHz |
| Propagation Delay | — | 1.48 ns (typ) |
| User I/Os | — | 488 |
| Core Supply Voltage | — | 1.8 V |
| Package Code | — | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Configuration | — | SRAM-based, serial or parallel (EPC) |
| Embedded Memory | — | EAB blocks (dual-port RAM with byte enables) |
| LVDS Support | — | True-LVDS channels integrated |
| MultiVolt I/O | — | 1.8 V, 2.5 V, 3.3 V interfaces |
| External Memory Interface | — | DDR SDRAM, QDR SRAM |
| JTAG Support | — | IEEE 1149.1 boundary-scan |