EP20K600CF672-3 vs EP20K600CEF672C7 Comparaison
Comparaison détaillée côte à côte de EP20K600CF672-3 par Intel et EP20K600CEF672C7 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CF672-3 | EP20K600CEF672C7 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $99,50 | $98,40 |
| Family | APEX 20KC | APEX 20KC (Enhanced Configuration) |
| Typical Gates | 600,000 | — |
| Maximum System Gates | 2,432,000 | — |
| Maximum Logic Elements | 2,432 | — |
| Embedded System Memory | 311,040 bits (380 Kbits ESB) | — |
| User I/O Pins | 488 | — |
| Boîtier | 672-ball FineLine BGA | 672-ball FineLine BGA (FC-FBGA) |
| Speed Grade | -3 | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm CMOS, all-layer copper |
| PLLs | 4 | — |
| Maximum Internal Frequency | 180 MHz (per APEX 20K family datasheet) | — |
| Configuration Modes | PS, PPS, PPA, JTAG, EPC2/EPC16 | — |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL-2/3, HSTL, LVDS, PCI | — |
| Type de montage | Surface Mount | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (commercial) |
| Statut RoHS | Lead-free / RoHS compliant (per Alibaba listing) | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | APEX 20KC |
| Device Type | — | FPGA / Loadable PLD |
| Logic Elements / Cells | — | 24,320 |
| Gate Count (typical) | — | 600,000 gates |
| Maximum Operating Frequency | — | 375.94 MHz |
| Propagation Delay | — | 1.48 ns (typ) |
| User I/Os | — | 488 |
| Core Supply Voltage | — | 1.8 V |
| Package Code | — | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Configuration | — | SRAM-based, serial or parallel (EPC) |
| Embedded Memory | — | EAB blocks (dual-port RAM with byte enables) |
| LVDS Support | — | True-LVDS channels integrated |
| MultiVolt I/O | — | 1.8 V, 2.5 V, 3.3 V interfaces |
| External Memory Interface | — | DDR SDRAM, QDR SRAM |
| JTAG Support | — | IEEE 1149.1 boundary-scan |