EP20K60EFC144-2 vs EP20K60EFC144-1 Comparación
Comparación detallada lado a lado de EP20K60EFC144-2 por Altera y EP20K60EFC144-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K60EFC144-2 | EP20K60EFC144-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $12,75 | $19,40 |
| Series | APEX-20K | APEX 20K |
| Family | APEX-20KE (Enhanced, 1.8 V core) | — |
| Typical Gates | 60,000 | 60,000 |
| Logic Elements | 2,560 | — |
| Total RAM Bits | 32,768 | — |
| User I/O | 92 to 93 | — |
| Core Supply Voltage | 1.71 V to 1.89 V | 1.8 V |
| Internal Frequency (max) | 160 MHz | — |
| Propagation Delay | 1.72 ns | 1.72 ns |
| Process Technology | 0.18 µm CMOS | — |
| Encapsulado | 144-LQFP (also referenced as 144-FBGA 13x13 in some sources) | 144-FBGA (Fine-pitch BGA) |
| Temperatura de funcionamiento | 0 °C to +85 °C (commercial) | 0 C to 85 C (Commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| JTAG Support | IEEE 1149.1 boundary scan | — |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ | — |
| Configuration Method | Serial/Parallel passive, JTAG, EPC companion | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Device Family | — | APEX 20KE |
| Logic Family | — | CMOS |
| Maximum System Gates | — | 256,000 |
| Macrocells | — | 256 |
| Maximum User I/Os | — | 93 (per datasheet; 196 max in 144-FBGA family datasheet) |
| Embedded Memory | — | 32,768 bits (2560 RAM blocks) |
| Maximum Internal Frequency | — | 160 MHz |
| Speed Grade | — | -1 |
| Package Pin Count | — | 144 balls |
| Programming Interface | — | JTAG / ByteBlaster / Altera Programming Unit |