EP20K60EFC144-2 vs EP20K60EFC144-1 Comparaison
Comparaison détaillée côte à côte de EP20K60EFC144-2 par Altera et EP20K60EFC144-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K60EFC144-2 | EP20K60EFC144-1 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $12,75 | $19,40 |
| Series | APEX-20K | APEX 20K |
| Family | APEX-20KE (Enhanced, 1.8 V core) | — |
| Typical Gates | 60,000 | 60,000 |
| Logic Elements | 2,560 | — |
| Total RAM Bits | 32,768 | — |
| User I/O | 92 to 93 | — |
| Core Supply Voltage | 1.71 V to 1.89 V | 1.8 V |
| Internal Frequency (max) | 160 MHz | — |
| Propagation Delay | 1.72 ns | 1.72 ns |
| Process Technology | 0.18 µm CMOS | — |
| Boîtier | 144-LQFP (also referenced as 144-FBGA 13x13 in some sources) | 144-FBGA (Fine-pitch BGA) |
| Température de fonctionnement | 0 °C to +85 °C (commercial) | 0 C to 85 C (Commercial) |
| Type de montage | Surface Mount | Surface Mount |
| JTAG Support | IEEE 1149.1 boundary scan | — |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ | — |
| Configuration Method | Serial/Parallel passive, JTAG, EPC companion | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Device Family | — | APEX 20KE |
| Logic Family | — | CMOS |
| Maximum System Gates | — | 256,000 |
| Macrocells | — | 256 |
| Maximum User I/Os | — | 93 (per datasheet; 196 max in 144-FBGA family datasheet) |
| Embedded Memory | — | 32,768 bits (2560 RAM blocks) |
| Maximum Internal Frequency | — | 160 MHz |
| Speed Grade | — | -1 |
| Package Pin Count | — | 144 balls |
| Programming Interface | — | JTAG / ByteBlaster / Altera Programming Unit |