EP20K60EFC324-3 vs EP20K60EFC324-2N Comparación
Comparación detallada lado a lado de EP20K60EFC324-3 por Intel y EP20K60EFC324-2N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K60EFC324-3 | EP20K60EFC324-2N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $58,40 | $52,73 |
| Series | APEX 20KE | APEX-20KE |
| Family | APEX 20K | APEX 20K |
| Logic Elements / Cells | 2560 | — |
| Total Gates | 60000 | — |
| User I/Os | 196 | — |
| Number of Logic Blocks / LABs | 256 | — |
| Embedded Memory (EAB/ESB) Bits | 24576 | — |
| Internal Frequency (max) | 160 MHz | 200 MHz |
| Propagation Delay | 1.72 ns | 1.72 ns |
| Peak Performance Frequency | 182 MHz | — |
| Core Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Voltage (VCCIO) | 3.3 V (3.0 V to 3.6 V) | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Logic Family | CMOS | — |
| Encapsulado / Carcasa | 324-FBGA (19x19 mm, 1.0 mm pitch) | 324-BGA (FineLine BGA, 19x19 mm) |
| Temperatura de funcionamiento | 0°C to +85°C (commercial) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programmable Type | In-system programmable (SRAM) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + passive serial | — |
| Estado RoHS | unknown | unknown |
| Number of Logic Elements/Cells | — | 2,560 |
| Total System Gates | — | 60,000 |
| Number of Logic Array Blocks (LABs/CLBs) | — | 2,560 |
| Total RAM Bits | — | 32,768 |
| Number of I/O | — | 196 |
| Core Voltage Supply | — | 1.71 V to 1.89 V (1.8 V typ.) |
| Operating Temperature Range (TJ) | — | 0 °C to 85 °C (commercial) |
| Supplier Device Package | — | 324-FBGA (19x19) |
| Architecture | — | MultiCore (LUT + ESB memory + product-term) |
| Configuration Method | — | Passive Serial / JTAG (IEEE 1149.1) |