EP20K60EFC324-3 vs EP20K60EFC324-2N Comparaison
Comparaison détaillée côte à côte de EP20K60EFC324-3 par Intel et EP20K60EFC324-2N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K60EFC324-3 | EP20K60EFC324-2N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $58,40 | $52,73 |
| Series | APEX 20KE | APEX-20KE |
| Family | APEX 20K | APEX 20K |
| Logic Elements / Cells | 2560 | — |
| Total Gates | 60000 | — |
| User I/Os | 196 | — |
| Number of Logic Blocks / LABs | 256 | — |
| Embedded Memory (EAB/ESB) Bits | 24576 | — |
| Internal Frequency (max) | 160 MHz | 200 MHz |
| Propagation Delay | 1.72 ns | 1.72 ns |
| Peak Performance Frequency | 182 MHz | — |
| Core Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Voltage (VCCIO) | 3.3 V (3.0 V to 3.6 V) | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Logic Family | CMOS | — |
| Boîtier / Format | 324-FBGA (19x19 mm, 1.0 mm pitch) | 324-BGA (FineLine BGA, 19x19 mm) |
| Température de fonctionnement | 0°C to +85°C (commercial) | — |
| Type de montage | Surface Mount | Surface Mount |
| Programmable Type | In-system programmable (SRAM) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + passive serial | — |
| Statut RoHS | unknown | unknown |
| Number of Logic Elements/Cells | — | 2,560 |
| Total System Gates | — | 60,000 |
| Number of Logic Array Blocks (LABs/CLBs) | — | 2,560 |
| Total RAM Bits | — | 32,768 |
| Number of I/O | — | 196 |
| Core Voltage Supply | — | 1.71 V to 1.89 V (1.8 V typ.) |
| Operating Temperature Range (TJ) | — | 0 °C to 85 °C (commercial) |
| Supplier Device Package | — | 324-FBGA (19x19) |
| Architecture | — | MultiCore (LUT + ESB memory + product-term) |
| Configuration Method | — | Passive Serial / JTAG (IEEE 1149.1) |