EP2A25F672C9 vs EP2A25F672ES Comparación
Comparación detallada lado a lado de EP2A25F672C9 por Altera y EP2A25F672ES por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A25F672C9 | EP2A25F672ES |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $700,00 | $198,00 |
| Family | APEX II | APEX II |
| Logic Elements (LE) | Approximately 25,000 | — |
| Macro Cells | 2432 | — |
| User I/O | 492 | — |
| Encapsulado | 672-ball FCBGA (FineLine BGA) | 672-ball FC-FBGA |
| Package Dimensions | 27 mm x 27 mm | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.15 µm CMOS |
| Logic Family | CMOS | — |
| Propagation Delay | 1.69 ns | — |
| Temperatura de funcionamiento | 0°C to 85°C (Commercial) | — |
| Tensión de alimentación | [DATA_NEEDED: core VCC voltage] | — |
| I/O Standards | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) | — |
| Configuration | Passive Serial, Passive Parallel Synchronous, JTAG | — |
| Embedded Memory | ESBs for dual-port RAM, ROM, FIFO | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | [DATA_NEEDED] | Compliant |
| Logic Elements | — | 24,320 |
| Maximum Gates | — | 900,000 |
| Embedded System Blocks (ESBs) | — | 24 |
| Maximum Embedded RAM | — | 1.4 Mbit |
| Maximum User I/O Pins | — | 492 |
| Core Voltage | — | 1.5 V |
| Maximum System Clock Frequency | — | 500 MHz |
| Number of PLLs | — | 4 |
| I/O Banks | — | 16 |
| Supported I/O Standards | — | LVTTL, LVCMOS, PCI, LVDS, LVPECL, HSTL |
| Configuration Mode | — | Serial / Parallel / JTAG |
| Rango de temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |