EP2A25F672I-9 vs EP2A25F672I6 Comparación
Comparación detallada lado a lado de EP2A25F672I-9 por Intel y EP2A25F672I6 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A25F672I-9 | EP2A25F672I6 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,00 | $178,00 |
| Family | APEX II | APEX II |
| Logic Elements (typical) | 25,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | — |
| Embedded System Blocks (ESB) Memory | 1,125 Kbits | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O pins] | — |
| Number of PLLs | 4 | — |
| Process Technology | 0.18 µm CMOS | 0.18 µm CMOS |
| Core Voltage | 1.5 V / 1.8 V (speed-grade dependent) | 1.5 V |
| Operating Temperature Grade | Industrial (-40 °C to +100 °C junction) | — |
| Speed Grade | -9 | 6 |
| Encapsulado | 672-pin FCBGA (FineLine BGA) | 672-ball FineLine BGA (FBGA-672) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Nivel de sensibilidad a la humedad (MSL) | 3 (per Vyrian listing) | — |
| Peak Reflow Temperature | 220 °C (per Vyrian listing) | — |
| Configuration Method | JTAG / serial configuration EPROM | External SRAM configuration device (EPC series) |
| Supported I/O Standards | LVTTL, LVCMOS, LVDS, PCI | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Legacy Status | Obsolete - consult Altera / Intel FPGA archive for documentation | — |
| Logic Elements (typical gates) | — | 25,000 |
| Fabric Architecture | — | SRAM-based LUT |
| Temperature Grade | — | Industrial (-40 °C to +100 °C ambient) |
| Embedded Memory | — | Embedded System Blocks (ESB), dual-port RAM / CAM |
| DSP Blocks | — | MultiCore dedicated multipliers |
| Boundary Scan | — | JTAG (IEEE 1149.1) compliant |
| Clock Management | — | Dedicated PLL / clock tree circuitry |
| I/O Bank Count | — | [DATA_NEEDED: number of user I/O banks] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Nivel MSL | — | [DATA_NEEDED: moisture sensitivity level] |