EP2A25F672I-9 vs EP2A25F672I6 Comparison
Detailed side-by-side comparison of EP2A25F672I-9 by Intel and EP2A25F672I6 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672I-9 | EP2A25F672I6 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $178.00 |
| Family | APEX II | APEX II |
| Logic Elements (typical) | 25,000 | β |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | β |
| Embedded System Blocks (ESB) Memory | 1,125 Kbits | β |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O pins] | β |
| Number of PLLs | 4 | β |
| Process Technology | 0.18 Β΅m CMOS | 0.18 Β΅m CMOS |
| Core Voltage | 1.5 V / 1.8 V (speed-grade dependent) | 1.5 V |
| Operating Temperature Grade | Industrial (-40 Β°C to +100 Β°C junction) | β |
| Speed Grade | -9 | 6 |
| Package | 672-pin FCBGA (FineLine BGA) | 672-ball FineLine BGA (FBGA-672) |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| Moisture Sensitivity Level (MSL) | 3 (per Vyrian listing) | β |
| Peak Reflow Temperature | 220 Β°C (per Vyrian listing) | β |
| Configuration Method | JTAG / serial configuration EPROM | External SRAM configuration device (EPC series) |
| Supported I/O Standards | LVTTL, LVCMOS, LVDS, PCI | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Legacy Status | Obsolete - consult Altera / Intel FPGA archive for documentation | β |
| Logic Elements (typical gates) | β | 25,000 |
| Fabric Architecture | β | SRAM-based LUT |
| Temperature Grade | β | Industrial (-40 Β°C to +100 Β°C ambient) |
| Embedded Memory | β | Embedded System Blocks (ESB), dual-port RAM / CAM |
| DSP Blocks | β | MultiCore dedicated multipliers |
| Boundary Scan | β | JTAG (IEEE 1149.1) compliant |
| Clock Management | β | Dedicated PLL / clock tree circuitry |
| I/O Bank Count | β | [DATA_NEEDED: number of user I/O banks] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| MSL Level | β | [DATA_NEEDED: moisture sensitivity level] |