EP2A40F672C6 vs EP2A40F672C8N Comparación
Comparación detallada lado a lado de EP2A40F672C6 por Altera y EP2A40F672C8N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A40F672C6 | EP2A40F672C8N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $105,00 | $122,00 |
| Family | APEX II | APEX II |
| Device | EP2A40 | — |
| Logic Elements (typical) | 40,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O count] | — |
| Encapsulado | 672-ball FineLine BGA (FBGA-672) | — |
| Speed Grade | C6 (commercial) | C8 |
| Temperatura de funcionamiento | Commercial (0C to +85C) | — |
| Process Technology | 0.18-micron CMOS | — |
| Configuration Memory | SRAM-based | — |
| JTAG Support | Yes (IEEE 1149.1) | — |
| PLL Support | Yes | — |
| Tipo de montaje | Surface Mount (BGA) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Lifecycle | Obsolete / EOL (per Intel/Altera product discontinuation notice) | — |
| Series | — | EP2A40 |
| Logic Family | — | CMOS |
| System Gates | — | 1.5 M |
| Logic Elements / Cells | — | 38,400 |
| Maximum Operating Frequency | — | 376 MHz |
| Propagation Delay | — | 1.55 ns |
| Technology Node | — | 0.15 µm |
| Process Feature | — | All-layer copper, up to 8 metal layers |
| Nominal Supply Voltage (VCCINT) | — | 1.5 V |
| Supply Voltage Range | — | 1.425 V to 1.575 V |
| User I/Os | — | 492 |
| Number of Pins / Balls | — | 672 |
| Package Type | — | FC-FBGA (FineLine BGA) |
| Package Dimensions | — | 27 x 27 mm |
| Ball Pitch | — | 1.0 mm |
| LVDS Data Rate | — | 1 Gbps |
| Embedded PLLs | — | 4 |
| Programming Interface | — | JTAG (IEEE 1149.1) |
| Operating Temperature (Commercial) | — | 0 °C to 85 °C |