EP2A70B724C7N vs EP2A70B724I-7 Comparación
Comparación detallada lado a lado de EP2A70B724C7N por Altera y EP2A70B724I-7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A70B724C7N | EP2A70B724I-7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $188,00 | $245,00 |
| Family | APEX II (EP2A70) | APEX II |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Technology | 0.15 µm CMOS | — |
| System Gates | 3,000,000 | — |
| Logic Cells / Logic Elements | 67,200 | — |
| Maximum Internal Frequency | 420 MHz | — |
| Propagation Delay (typ.) | 2.17 ns | — |
| User I/O Pins | 536 | — |
| Macrocells (memory blocks reference) | 16 | — |
| Core Supply Voltage | 1.5 V nominal | — |
| I/O Supply Voltage | MultiVolt (1.5V / 1.8V / 2.5V / 3.3V / 5V tolerant) | — |
| Temperatura de funcionamiento | 0 °C to +85 °C (Commercial) | — |
| Encapsulado | 724-pin FCBGA (Flip-Chip BGA) | BGA-724 |
| Ball Pitch | 1.27 mm | — |
| Seated Height | 3.5 mm | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Configuration Method | JTAG, Passive Serial (PS), Fast Passive Parallel (FPP) | — |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| Embedded Memory | Embedded System Blocks (ESBs) - dual-port RAM / ROM / CAM | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS] |
| Logic Elements | — | 70,000 (EP2A70 family variant) |
| Typical Gates | — | [DATA_NEEDED: typical gate count] |
| Maximum User I/O | — | [DATA_NEEDED: max user I/O] |
| Embedded System Blocks | — | [DATA_NEEDED: ESB count] |
| Temperature Grade | — | Industrial |
| Speed Grade | — | -7 |
| Supply Voltage (Core) | — | [DATA_NEEDED: core VCC] |
| I/O Standards | — | LVTTL, LVCMOS, PCI, SSTL, GTL+ |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Active Serial |
| Process Technology | — | CMOS |
| Peak Reflow Temperature | — | 220 C |