EP2AGZ350FF35I3G vs EP2AGZ350FF35I3 Comparación
Comparación detallada lado a lado de EP2AGZ350FF35I3G por Intel y EP2AGZ350FF35I3 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2AGZ350FF35I3G | EP2AGZ350FF35I3 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.850,00 | $4.409,18 |
| Family | Arria II GZ | — |
| Logic Elements | 350,000 | — |
| Embedded Memory (Bits) | 21,270,528 | — |
| Embedded RAM | 17.4 Mbit | — |
| User I/O | 554 | — |
| Encapsulado | 1152-BBGA, FCBGA | 1152-ball FCBGA (FF35) |
| Speed Grade | I3 | — |
| Temperatura de funcionamiento | -40C to +100C (Industrial) | — |
| Process Node | 40 nm | 40 nm |
| Transceivers | Multi-gigabit transceivers (per Arria II GZ family) | Up to 16 channels |
| DSP Blocks | Yes, variable-precision | — |
| Memory Interfaces | DDR3, DDR2, QDRII+, RLDRAM II | — |
| Hard IP | PCIe Gen2, 10GbE MAC | — |
| Configuration | Passive Serial, Fast Passive Parallel, JTAG | — |
| Estado RoHS | Compliant (Pb-free, G) | Compliant per distributor listings |
| Lead-Free | Yes | — |
| Nivel MSL | [DATA_NEEDED: MSL Level] | 3 (per typical Altera FCBGA handling) |
| Tensión de alimentación | [DATA_NEEDED: Core/IO supply] | — |
| Series | — | Arria II GZ |
| Logic Elements (LE) | — | 348,500 |
| Embedded Memory Bits | — | 21,270,528 bits |
| Embedded Memory (M9K/M144K) | — | [DATA_NEEDED: block count and distribution] |
| Maximum User I/O | — | 554 |
| Transceiver Data Rate | — | 6.375 Gbps |
| DSP Blocks (18x19 multipliers) | — | [DATA_NEEDED: exact multiplier count, datasheet lists up to ~1,368] |
| Ball Pitch | — | 1.0 mm |
| Operating Temperature Grade | — | Industrial (-40C to +100C Tj) |
| Supply Voltage (Core) | — | 0.9 V typical [DATA_NEEDED: full range from datasheet] |
| Configuration Method | — | FPGA configuration via Altera Quartus II |
| Hard IP Blocks | — | PCIe Gen2 hard IP, memory controllers, PLLs |