EP2S130F1020I4 vs EP2S130F1020C5N Comparación
Comparación detallada lado a lado de EP2S130F1020I4 por Intel y EP2S130F1020C5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2S130F1020I4 | EP2S130F1020C5N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.395,00 | $1.320,00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Equivalent LEs | ~180,000 | — |
| Adaptive Logic Modules (ALMs) | 53,016 | 6627 LABs (per Jotrin listing) |
| Embedded Memory (bits) | 6,747,840 | — |
| Embedded Memory (M512 blocks) | 530 | — |
| Embedded Memory (M4K blocks) | 768 | — |
| Embedded Memory (M-RAM blocks) | 4 | — |
| Embedded 18x18 Multipliers | 504 | — |
| DSP Blocks | 48 | — |
| User I/O Pins | 742 | — |
| User I/O Banks | 12 | — |
| Encapsulado | 1020-ball FC-FBGA (33x33 mm) | 1020-ball FC-FBGA (33x33 mm) |
| Process Node | 90 nm CMOS, all-layer copper | — |
| Core Voltage (VCCINT) | 1.2 V | — |
| Speed Grade | I (industrial performance) | — |
| Device Revision | 4 | — |
| Temperatura de unión de funcionamiento | -40C to +100C (industrial) | — |
| Configuration Scheme | Fast Passive Parallel x8, Passive Serial, JTAG | — |
| Tipo de montaje | Surface Mount (FC-FBGA) | Surface Mount |
| Estado RoHS | Compliant (per distributor listings) | [DATA_NEEDED: rohs status] |
| Total Memory Bits | — | 6,747,840 bits |
| User I/Os | — | 734 |
| Process Technology | — | 90 nm |
| Core Supply Voltage (VCCINT) | — | 1.15 V to 1.25 V |
| Maximum Internal Frequency | — | 609.76 MHz |
| Temperatura de funcionamiento | — | Commercial (0C to +85C, C5 grade) |
| Temperature Grade | — | C5 (other - per Partstack) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| PLLs | — | 4 (typical Stratix II feature) |
| Global Clock Networks | — | 16 (typical Stratix II feature) |
| Configuration Method | — | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | — | Republic of Korea (per GlobalSpec) |
| ECCN | — | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | — | 2023 (per GlobalSpec) |