EP2S130F1020I4 vs EP2S130F1020C5N 对比

详细并排对比 EP2S130F1020I4 出自 Intel 和 EP2S130F1020C5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S130F1020I4 EP2S130F1020C5N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $1,395.00 $1,320.00
Family Stratix II Stratix II
Logic Elements 132,540 132,540
Equivalent LEs ~180,000 —
Adaptive Logic Modules (ALMs) 53,016 6627 LABs (per Jotrin listing)
Embedded Memory (bits) 6,747,840 —
Embedded Memory (M512 blocks) 530 —
Embedded Memory (M4K blocks) 768 —
Embedded Memory (M-RAM blocks) 4 —
Embedded 18x18 Multipliers 504 —
DSP Blocks 48 —
User I/O Pins 742 —
User I/O Banks 12 —
封装 1020-ball FC-FBGA (33x33 mm) 1020-ball FC-FBGA (33x33 mm)
Process Node 90 nm CMOS, all-layer copper —
Core Voltage (VCCINT) 1.2 V —
Speed Grade I (industrial performance) —
Device Revision 4 —
工作结温 -40C to +100C (industrial) —
Configuration Scheme Fast Passive Parallel x8, Passive Serial, JTAG —
安装类型 Surface Mount (FC-FBGA) Surface Mount
RoHS 状态 Compliant (per distributor listings) [DATA_NEEDED: rohs status]
Total Memory Bits — 6,747,840 bits
User I/Os — 734
Process Technology — 90 nm
Core Supply Voltage (VCCINT) — 1.15 V to 1.25 V
Maximum Internal Frequency — 609.76 MHz
工作温度 — Commercial (0C to +85C, C5 grade)
Temperature Grade — C5 (other - per Partstack)
Lead-Free — [DATA_NEEDED: lead-free status]
PLLs — 4 (typical Stratix II feature)
Global Clock Networks — 16 (typical Stratix II feature)
Configuration Method — Serial/Parallel via Quartus II (typical Stratix II)
Country of Origin — Republic of Korea (per GlobalSpec)
ECCN — 3A001.a.7.a (per GlobalSpec)
Estimated EOL Date — 2023 (per GlobalSpec)

数据手册与资源

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