EP2S30F672I4 vs EP2S30F672C4 Comparación
Comparación detallada lado a lado de EP2S30F672I4 por Intel y EP2S30F672C4 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2S30F672I4 | EP2S30F672C4 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $695,00 | $498,43 |
| Series | Stratix II | Stratix II |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| Logic Elements | 33880 | — |
| Logic Array Blocks (LABs) | 1694 | — |
| Total RAM Bits | 1369728 | 1,369,728 |
| Number of I/O | 500 | 500 |
| DSP Blocks | 12 (per datasheet, family range) | — |
| Number of PLLs | 6 | [DATA_NEEDED: PLL count for S30 tier] |
| Voltage - Supply | 1.2 V core, separate I/O bank VCCIO | — |
| Temperatura de funcionamiento | -40C to +100C (Industrial) | 0C to +85C (commercial, 'C' speed grade) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Encapsulado / Carcasa | 672-BBGA, FCBGA (FBGA-672) | — |
| Package Dimensions | 35 x 35 mm | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 90 nm CMOS | 90 nm |
| Configuration | JTAG, serial, parallel (Stratix II scheme) | — |
| Nivel MSL | 3 (per JEDEC J-STD-020) | — |
| Estado RoHS | [DATA_NEEDED: confirm RoHS compliance on part label] | Compliant |
| Logic Elements / Cells | — | 33,880 |
| Encapsulado | — | 672-BBGA, FCBGA (27x27 mm) |
| Core Voltage - Supply | — | 1.15 V to 1.25 V |
| Maximum Core Frequency (datasheet benchmark) | — | 711 MHz |
| Embedded DSP Blocks | — | 16 (Stratix II S30 tier) |
| Number of Global Clock Networks | — | [DATA_NEEDED: global clock network count] |
| Lead-Free | — | Yes |