EP2S90F1020I4N vs EP2S90F1020C3N Comparación
Comparación detallada lado a lado de EP2S90F1020I4N por Intel y EP2S90F1020C3N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP2S90F1020C3N - 90nm Stratix II FPGA 90,960 LEs FC-FBGA-1020 | Altera
EP2S90F1020C3N ⚠ Última compraComparación de especificaciones
| Parámetro | EP2S90F1020I4N | EP2S90F1020C3N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.995,00 | $1.995,00 |
| Family | Stratix II | Stratix II (EP2S90) |
| Logic Elements | 90,960 | 90,960 |
| Logic Array Blocks (LABs) | 4548 | — |
| Embedded Memory Bits | 4,520,488 | — |
| User I/Os | 758 | — |
| Encapsulado | 1020-ball FineLine BGA | — |
| Core Voltage | 1.2 V | — |
| Temperatura de funcionamiento | -40C to +100C (Industrial) | 0C to +85C (commercial grade) |
| Process Technology | 90 nm | 90 nm CMOS |
| Embedded DSP Blocks | Yes (DSP blocks) | — |
| User I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Configuration Method | Serial/Parallel via EPCS or JTAG | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Compliant |
| Nivel MSL | [DATA_NEEDED: MSL rating] | 3 (per JEDEC J-STD-020) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Logic Architecture | ALM (Adaptive Logic Module) | — |
| Series | — | Stratix II |
| LABs (Logic Array Blocks) | — | 4,548 |
| Total RAM Bits | — | 4,520,488 |
| User I/O Count | — | 758 |
| Supply Voltage - Core | — | 1.15 V to 1.25 V (1.2 V nominal) |
| Speed Grade | — | C3 (commercial, slowest) |
| Encapsulado / Carcasa | — | 1020-BBGA, FC-FBGA |
| Supplier Device Package | — | 1020-FBGA (33 x 33 mm) |
| DSP Block Count | — | [DATA_NEEDED: 18x18 multiplier count] |
| Embedded Transceivers | — | [DATA_NEEDED: number of high-speed transceivers] |
| Maximum User I/O Frequency | — | [DATA_NEEDED: LVDS / DDR max rate] |
| Programming Tool | — | Altera Quartus II |