EP3CLS100U484C7N vs EP3C80U484C7N Comparación
Comparación detallada lado a lado de EP3CLS100U484C7N por Altera y EP3C80U484C7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP3CLS100U484C7N | EP3C80U484C7N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $412,65 | $0,00 |
| Device Family | Cyclone III LS | — |
| Logic Elements | 100,448 | — |
| Embedded Memory | 4,451,328 bits (4.4 Mbit) | 2,810,880 bits |
| User I/O Pins | 278 | — |
| Encapsulado | 484-ball FBGA (UBGA) | — |
| Process Technology | 65 nm TSMC low-power | 65 nm |
| Core Supply Voltage | 1.2 V | — |
| Speed Grade | 7 (commercial) | — |
| Maximum Internal Frequency | 437.5 MHz | — |
| Temperatura de funcionamiento | 0C to +85C (commercial) | — |
| Configuration Mode | AS / AP / PS / JTAG | — |
| DSP Blocks (18x18 multipliers) | [DATA_NEEDED: DSP block count] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| I/O Banks | 8 | — |
| Tipo de montaje | Surface Mount (BGA) | — |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Product Family | — | Cyclone III |
| Logic Cell Count | — | 81,264 cells |
| User I/O Count | — | 295 I/O |
| Frecuencia de reloj máxima | — | 437.5 MHz |
| Tensión de alimentación | — | 1.2 V |
| Terminal Count | — | 484 terminals |
| Package Code | — | FBGA |
| Package Description | — | 484-UBGA |
| Package Shape | — | Rectangular |
| Terminal Form | — | Ball |
| Temperature Grading | — | Other |
| Estilo de montaje | — | Surface Mount |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |