EP3CLS70F780I7N vs EP3CLS70F780C7 Comparación
Comparación detallada lado a lado de EP3CLS70F780I7N por Intel y EP3CLS70F780C7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP3CLS70F780I7N - 70,208 Logic Elements FPGA | Intel | Embedded Systems
EP3CLS70F780I7N ✓ Activo
Comparación de especificaciones
| Parámetro | EP3CLS70F780I7N | EP3CLS70F780C7 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $880,00 | $350,00 |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Series | Cyclone III LS | — |
| Logic Elements | 70,208 | 70,208 |
| Embedded Memory | 3,068,928 bits | — |
| Maximum User I/O | 413 pins | — |
| Tensión de alimentación | 1.2 V | — |
| Temperature Grade | Industrial | — |
| Package Type | BGA | — |
| Package Pin Count | 780 balls | — |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Configuration Technology | SRAM-based FPGA | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature] | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | unknown | Compliant |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | Cyclone III LS |
| Embedded Memory Bits | — | 3,068,928 |
| User I/O Pins | — | 413 |
| Total I/O Pins | — | 780 (FBGA package) |
| Process Technology | — | 65 nm |
| Core Supply Voltage (VCCINT) | — | 1.2 V |
| Operating Frequency (max) | — | 437.5 MHz |
| Encapsulado | — | 780-ball FBGA |
| Speed Grade | — | C7 (commercial, low power) |
| Security Features | — | AES-256 bitstream encryption, JTAG protection, volatile key storage |
| Embedded Multipliers | — | 18 x 18 multipliers (DSP blocks) |
| PLLs | — | Yes (per PLL specification) |